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LTC4300-1/ltc4300-2 1 sn430012 430012fs the ltc ? 4300 series hot swappable 2-wire bus buffers allow i/o card insertion into a live backplane without cor- ruption of the data and clock busses. when the connection is made, the LTC4300-1/ltc4300-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. rise-time accelerator circuitry* allows the use of weaker dc pull-up currents while still meeting rise-time requirements. during insertion, the sda and scl lines are precharged to 1v to minimize bus disturbances. the LTC4300-1 incorporates a cmos threshold digital enable input pin, which forces the part into a low current mode when driven to ground and sets normal operation when driven to v cc . it also includes an open drain ready output pin, which indicates that the backplane and card sides are connected together. the ltc4300-2 replaces the enable pin with a dedicated supply voltage pin, v cc2 , for the card side, providing level shifting between 3.3v and 5v systems. both the backplane and card may be powered with supply voltages ranging from 2.7v to 5.5v, with no contraints on which supply voltage is higher. the ltc4300-2 also replaces the ready pin with a digital cmos input pin, acc, which enables and disables the rise-time accelerator currents. the ltc4300 is available in a small 8-pin msop package. n hot board insertion n servers n capacitance buffer/bus extender n desktop computer , ltc and lt are registered trademarks of linear technology corporation. n bidirectional buffer for sda and scl lines increases fanout n prevents sda and scl corruption during live board insertion and removal from backplane n isolates input sda and scl lines from output n compatible with i 2 c tm , i 2 c fast mode and smbus standards (up to 400khz operation) n small msop 8-pin package n low i cc chip disable: <1 m a (LTC4300-1) n ready open drain output (LTC4300-1) n 1v precharge on all sda and scl lines n supports clock stretching, arbitration and synchronization n 5v to 3.3v level translation (ltc4300-2) n high impedance sda, scl pins for v cc = 0v hot swappable 2-wire bus buffers i 2 c is a trademark of philips electronics n. v. *u.s. patent no. 6,650,174 r1 24k v cc 3.3v r2 24k enable sclin sclout sdain sdaout 15 4 67 32 8 gnd LTC4300-1 ready c1 0.01 f c2* c4* c5* c3* 4300-1/2 ta01 r3 24k r4 24k *capacitors not required if bus is sufficiently loaded applicatio s u features typical applicatio u descriptio u inputCoutput connection t plh output side 50pf input side 150pf
LTC4300-1/ltc4300-2 2 sn430012 430012fs v cc to gnd .................................................... C 0.5 to 7v v cc2 to gnd (ltc4300-2) ............................. C 0.5 to 7v sdain, sclin, sdaout, sclout ................. C 0.5 to 7v ready, enable (LTC4300-1) ....................... C 0.5 to 7v acc (ltc4300-2) .......................................... C 0.5 to 7v operating temperature range LTC4300-1c/ltc4300-2c ....................... 0 c to 70 c LTC4300-1i/ltc4300-2i .................... C 40 c to 85 c storage temperature range ................. C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number ms8 part marking t jmax = 125 c, q ja = 200 c/w consult ltc marketing for parts specified with wider operating temperature ranges. ltub ltuc ltvj ltvk LTC4300-1cms8 LTC4300-1ims8 ltc4300-2cms8 ltc4300-2ims8 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specfications are at t a = 25 c. v cc = 2.7v to 5.5v, unless otherwise noted. 1 2 3 4 enable/v cc2 * sclout sclin gnd 8 7 6 5 v cc sdaout sdain ready/acc* top view ms8 package 8-lead plastic msop *ltc4300-2 symbol parameter conditions min typ max units power supply v cc positive supply voltage l 2.7 5.5 v i cc supply current v cc = 5.5v, v sdain = v sclin = 0v, LTC4300-1 l 2.8 6 ma i sd supply current in shutdown mode v enable = 0v, LTC4300-1 0.1 m a v cc2 card side supply voltage ltc4300-2 l 2.7 5.5 v i vcc1 v cc supply current v sdain = v sclin = 0v, v cc1 = v cc2 = 5.5v, 1.8 3.6 ma ltc4300-2 i vcc2 v cc2 supply current v sdaout = v sclout = 0v, v cc1 = v cc2 = 5.5v, 1.2 2.4 ma ltc4300-2 start-up circuitry v pre precharge voltage sda, scl floating l 0.8 1.0 1.2 v t idle bus idle time l 50 95 150 m s v en enable threshold voltage LTC4300-1 0.5 ? v cc 0.9 ? v cc v v dis disable threshold voltage LTC4300-1, enable pin 0.1 ? v cc 0.5 ? v cc v i en enable input current enable from 0v to v cc , LTC4300-1 0.1 1 m a t phl enable delay, on-off LTC4300-1 100 ns ready delay, off-on LTC4300-1 10 ns t plh enable delay, off-on LTC4300-1 80 m s ready delay, on-off LTC4300-1 10 m s i off ready off state leakage current LTC4300-1 0.1 m a v ol ready output low voltage i pullup = 3ma, LTC4300-1 l 0.4 v
LTC4300-1/ltc4300-2 3 sn430012 430012fs note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired note 2: i pullupac varies with temperature and v cc voltage, as shown in the typical performance characteristics section. note 3: the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pullup resistor and v cc voltage is shown in the typical performance characteristics section. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specfications are at t a = 25 c. v cc = 2.7v to 5.5v, unless otherwise noted. symbol parameter conditions min typ max units rise-time accelerators i pullupac transient boosted pull-up current positive transition on sda,scl, v cc = 2.7v, 1 2 ma slew rate = 1.25v/ m s (note 2), ltc4300-2, acc = 0.7 ? v cc2 , v cc2 = 2.7v v accdis accelerator disable threshold ltc4300-2 0.3 ? v cc2 0.5 ? v cc2 v v accen accelerator enable threshold ltc4300-2 0.5 ? v cc2 0.7 ? v cc2 v i vacc acc input current ltc4300-2 0.1 1 m a t pdoff acc delay, on/off ltc4300-2 5 ns input-output connection v os input-output offset voltage 10k to v cc on sda, scl, v cc = 3.3v (note 3), l 0 75 150 mv ltc4300-2, v cc2 = 3.3v, v in = 0.2v f scl, sda operating frequency guaranteed by design, not subject to test 0 400 khz c in digital input capacitance guaranteed by design, not subject to test 10 pf v ol output low voltage, input = 0v sda, scl pins, i sink = 3ma, v cc = 2.7v, l 0 0.4 v v cc2 = 2.7v, ltc4300-2 i leak input leakage current sda, scl pins = v cc = 5.5v, 5 m a ltc4300-2, v cc2 = 5.5v timing characteristics f i2c i 2 c operating frequency (note 4) 0 400 khz t buf bus free time between stop (note 4) 1.3 m s and start condition t hd,sta hold time after (repeated) (note 4) 0.6 m s start condition t su,sta repeated start condition setup time (note 4) 0.6 m s t su,sto stop condition setup time (note 4) 0.6 m s t hd, dat data hold time (note 4) 300 ns t su, dat data setup time (note 4) 100 ns t low clock low period (note 4) 1.3 m s t high clock high period (note 4) 0.6 m s t f clock, data fall time (notes 4, 5) 20 + 0.1 ? c b 300 ns t r clock, data rise time (notes 4, 5) 20 + 0.1 ? c b 300 ns note 4: guaranteed by design, not subject to test. note 5: c b = total capacitance of one bus line in pf.
LTC4300-1/ltc4300-2 4 sn430012 430012fs 50 25 0 25 50 75 100 temperature ( c) i pullupac (ma) 4300-1/2 g03 12 10 8 6 4 2 0 v cc = 2.7v v cc = 5v v cc = 3v r pullup ( ) 0 10,000 20,000 30,000 40,000 v out ?v in (mv) 4300-1/2 g04 300 250 200 150 100 50 0 v cc = 3.3v v cc = 5v t a = 25 c v in = 0v i pullupac vs temperature connection circuitry v out C v in typical perfor a ce characteristics uw 50 25 0 25 50 75 100 temperature ( c) t phl (ns) 4300-1/2 g02 100 80 60 40 20 0 v cc = 2.7v v cc = 3.3v v cc = 5.5v c in = c out = 100pf r pullupin = r pullupout = 10k input C output t phl vs temperature (LTC4300-1) 50 25 0 25 50 75 100 temperature ( c) i cc (ma) 4300-1/2 g01 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 v cc = 5.5v v cc = 2.7v i cc vs temperature (LTC4300-1)
LTC4300-1/ltc4300-2 5 sn430012 430012fs enable/v cc2 (pin 1): chip enable pin/card supply volt- age. for the LTC4300-1, this is a digital cmos threshold input pin. grounding this pin puts the part in a low current (<1 m a) mode. it also disables the rise-time accelerators, disables the bus precharge circuitry, drives ready low, isolates sdain from sdaout and isolates sclin from sclout. drive enable all the way to v cc for normal operation. connect enable to v cc if this feature is not being used. for the ltc4300-2, this is the supply voltage for the devices on the card i 2 c busses. connect pull-up resistors from sdaout and sclout to this pin. place a bypass capacitor of at least 0.01 m f close to this pin for best results. sclout (pin 2): serial clock output. connect this pin to the scl bus on the card. see figures 3 and 4 for bus pull- up resistance and capacitance requirements. sclin (pin 3): serial clock input. connect this pin to the scl bus on the backplane. see figures 3 and 4 for bus pull- up resistance and capacitance requirements. gnd (pin 4): ground. connect this pin to a ground plane for best results. ready/acc (pin 5): connection flag/rise-time accel- erator control. for the LTC4300-1, this is an open-drain nmos output which pulls low when either enable is low or the start-up sequence described in the operation sec- tion has not been completed. ready goes high when enable is high and start-up is complete. connect a 10k resistor from this pin to v cc to provide the pull up. for the ltc4300-2, this is a cmos threshold digital input pin that enables and disables the rise-time accelerators on all four sda and scl pins. drive acc all the way to the v cc2 supply voltage to enable all four accelerators; drive acc to ground to turn them off. sdain (pin 6): serial data input. connect this pin to the sda bus on the backplane. see figures 3 and 4 for bus pull-up resistance and capacitance requirements. sdaout (pin 7): serial data output. connect this pin to the sda bus on the card. see figures 3 and 4 for bus pull- up resistance and capacitance requirements. v cc (pin 8): main input power supply from backplane. this is the supply voltage for the devices on the backplane i 2 c busses. connect pull-up resistors from sdain and sclin to this pin. place a bypass capacitor of at least 0.01 m f close to this pin for best results. pi fu ctio s uuu
LTC4300-1/ltc4300-2 6 sn430012 430012fs 100k rch1 100k rch3 + 5 + 0.5pf ready 1 enable uvlo 3 sclin 4300-1 bd connect stop bit and bus idle 4 4 gnd connect 20pf rd s qb 0.5 a 0.55v cc / 0.45v cc + + 0.55v cc / 0.45v cc 2ma 95 s delay backplane-to-card connection connect connect 2 sclout 6 sdain backplane-to-card connection connect connect 7 sdaout 8 v cc 1v precharge 100k rch2 100k rch4 slew rate dectector 2ma slew rate dectector 2ma slew rate dectector 2ma slew rate dectector connect enable 2-wire bus buffer and hot swap tm controller block diagra w hot swap is a trademark of linear technology corporation. (LTC4300-1)
LTC4300-1/ltc4300-2 7 sn430012 430012fs block diagra w (ltc4300-2) 100k rch1 100k rch3 + + 0.5pf uvlo 3 sclin 4300-2 bd connect connect stop bit and bus idle 4 4 gnd 20pf rd s qb 0.5 a 0.55v cc / 0.45v cc + + 0.55v cc2 / 0.45v cc2 2ma 95 s delay backplane-to-card connection connect connect 2 sclout 6 sdain 8 v cc backplane-to-card connection connect connect 7 sdaout 1 v cc2 5 acc 1v precharge 100k rch2 100k rch4 connect slew rate dectector 2ma slew rate dectector 2ma slew rate dectector acc acc 2ma slew rate dectector 2-wire bus buffer and hot swap controller
LTC4300-1/ltc4300-2 8 sn430012 430012fs operatio u the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. input to output offset voltage when a logic low voltage, v low1 , is driven on any of the ltc4300s data or clock pins, the ltc4300 regulates the voltage on the other side of the chip (call it v low2 ) to a slightly higher voltage, as directed by the following equation: v low2 = v low1 + 50mv + (v cc /r) ? 100 where r is the bus pull-up resistance in ohms. for ex- ample, if a device is forcing sdaout to 10mv and if v cc = 3.3v and the pull-up resistor r on sdain is 10k, then the voltage on sdain = 10mv + 50mv + (3.3/10000) ? 100 = 93mv. see the typical performance characteristics section for curves showing the offset voltage as a function of v cc and r. propagation delays during a rising edge, the rise-time on each side is deter- mined by the combined pull-up current of the ltc4300 boost current and the bus resistor and the equivalent capacitance on the line. if the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. this effect is displayed in figure 1 for v cc = 3.3v and a 10k pull-up resistor on each side (50pf on one side and 150pf on the other). since the output side has less capacitance than the input, it rises faster and the effective t plh is negative. there is a finite propagation delay, t phl , through the connection circuitry for falling waveforms. figure 2 shows the falling edge waveforms for the same v cc , pull-up resistors and equivalent capacitance conditions as used in figure 1. an external nmos device pulls down the voltage on the side with 150pf capacitance; the ltc4300 pulls down the voltage on the opposite side, with a delay of 55ns. this delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. the typical performance characteristics section shows t phl start-up when the ltc4300 first receives power on its v cc pin, either during power-up or during hot swapping, it starts in an undervoltage lockout (uvlo) state, ignoring any activ- ity on the sda and scl pins until v cc rises above 2.5v. for the ltc4300-2, the part also waits for v cc2 to rise above 2v. this ensures that the part does not try to function until it has enough voltage to do so. during this time, the 1v precharge circuitry is also active and forces 1v through 100k nominal resistors to the sda and scl pins. because the i/o card is being plugged into a live backplane, the voltage on the backplane sda and scl busses may be anywhere between 0v and v cc . precharging the scl and sda pins to 1v minimizes the worst-case voltage differential these pins will see at the moment of con- nection, therefore minimizing the amount of disturbance caused by the i/o card. once the ltc4300 comes out of uvlo, it assumes that sdain and sclin have been hot swapped into a live system and that sdaout and sclout are being powered up at the same time as itself. therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. when either one occurs, the part also verifies that both the sdaout and sclout voltages are high. when all of these condi- tions are met, the input-to-output connection circuitry is activated, joining the sda and scl busses on the i/o card with those on the backplane. connection circuitry once the connection circuitry is activated, the functional- ity of the sdain and sdaout pins is identical. a low forced on either pin at any time results in both pin voltages being low. sdain and sdaout enter a logic high state only when all devices on both sdain and sdaout force a high. the same is true for sclin and sclout. this important fea- ture ensures that clock stretching, clock arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the ltc4300. another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. because of this isolation,
LTC4300-1/ltc4300-2 9 sn430012 430012fs as a function of temperature and voltage for 10k pull-up resistors and 100pf equivalent capacitance on both sides of the part. by comparison with figure 2, the v cc = 3.3v curve shows that increasing the capacitance from 50pf to 150pf results in a t phl increase from 55ns to 75ns. larger output capacitances translate to longer delays (up to 150ns). users must quantify the difference in propagation times for a rising edge vs a falling edge in their systems and adjust setup and hold times accordingly. rise-time accelerators once connection has been established, rise-time accelera- tor circuits on all four sda and scl pins are activated. these allow the user to choose weaker dc pull-up currents on the bus, reducing power consumption while still meet- ing system rise-time requirements. during positive bus transitions, the ltc4300 switches in 2ma of current to quickly slew the sda and scl lines once their dc voltages exceed 0.6v. using a general rule of 20pf of capacitance for every device on the bus (10pf for the device and 10pf for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25v/ m s to guarantee activation of the accelerators. for example, assume an smbus system with v cc = 3v, a 10k pull-up resistor and equivalent bus capacitance of 200pf. the rise-time of an smbus system is calculated from (v il(max) C 0.15v) to (v ih(min) + 0.15v), or 0.65v to 2.25v. it takes an rc circuit 0.92 time constants to traverse this voltage for a 3v supply; in this case, 0.92 ? (10k ? 200pf) = 1.85 m s. thus, the system exceeds the maximum allowed rise-time of 1 m s by 85%. however, using the rise-time accelerators, which are activated at a dc threshold of below 0.65v, the worst-case rise-time is: (2.25v C 0.65v) ? 200pf/1ma = 320ns, which meets the 1 m s rise-time requirement. ready digital output (LTC4300-1) this pin provides a digital flag which is low when either enable is low or the start-up sequence described earlier in this section has not been completed. ready goes high when enable is high and start-up is complete. the pin is driven by an open drain pull-down capable of sinking 3ma while holding 0.4v on the pin. connect a resistor of 10k to v cc to provide the pull-up. this feature is available for the LTC4300-1 only. enable low current disable (LTC4300-1) grounding the enable pin disconnects the backplane side from the card side, disables the rise-time accelera- tors, drives ready low, disables the bus precharge cir- cuitry and puts the part in a near-zero current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete (as described in the start-up section) before reconnecting the two sides. this feature is available for the LTC4300-1 only. acc boost current enable (ltc4300-2) users having lightly loaded systems may wish to disable the rise-time accelerators. driving this pin to ground turns off the rise-time accelerators on all four sda and scl pins. driving this pin to the v cc2 voltage enables normal opera- tion of the rise-time accelerators, as described in the rise- time accelerators section above. this feature is available for the ltc4300-2 only. operatio u figure 1. inputCoutput connection t plh figure 2. inputCoutput connection t phl output side 50pf input side 150pf input side 150pf output side 50pf
LTC4300-1/ltc4300-2 10 sn430012 430012fs resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25v/ m s on the sda and scl pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value r using the formula: r (v cc(min) C 0.6) (800,000) / c where r is the pull-up resistor value in ohms, v cc(min) is the minimum v cc voltage and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r 16k for v cc = 5.5v maximum, r 24k for v cc = 3.6v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. see the curves in figures 3 and 4 for guidance in resistor pull-up selection. minimum sda and scl capacitance requirements the ltc4300 i/o connection circuitry requires a minimum capacitance loading on the sda and scl pins in order to function properly. the value of this capacitance is a function of v cc and the bus pull-up resistance. estimate the bus capacitance on both the backplane and the card data and clock busses, and refer to figures 3 and 4 to choose appropriate pull-up resistor values. note from the applicatio s i for atio wu u u figures that 5v systems must have at least 47pf capaci- tance on their busses and 3.3v systems must have at least 22pf capacitance for proper operation of the ltc4300. for applications with less capacitance, add a capacitor to ground to ensure these minimum capacitance conditions. hot swapping and capacitance buffering application figures 5 through 8 illustrate the usage of the ltc4300 in applications that take advantage of both its hot swapping and capacitance buffering features. in all of these applica- tions, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. placing a ltc4300 on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the ltc4300 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the ltc4300, which is less than 10pf. figure 5 shows the LTC4300-1 in a compactpci tm con- figuration. connect v cc to the output of one of the compactpci power supply hot swap circuits and connect enable to the short board enable pin. v cc is monitored by a filtered uvlo circuit. with the v cc voltage powering up after all other pins have established connection, the uvlo circuit ensures that the backplane and card data and clock busses are not connected until the transients asso- figure 3. bus requirements for 3.3v systems figure 4. bus requirements for 5v systems c bus (pf) 0 r pullup (k ) 4300-1/2 f03 30 25 20 15 10 5 0 100 200 300 400 r max = 24k rise-time > 300ns recommended pull-up c bus (pf) 0 r pullup (k ) 4300-1/2 f04 0 0 5 10 15 20 100 200 300 400 rise-time > 300ns recommended pull-up r max = 16k compactpci is a trademark of the pci industrial computer manufacturers group.
LTC4300-1/ltc4300-2 11 sn430012 430012fs applicatio s i for atio wu u u ciated with hot swapping have settled. owing to their small capacitance, the sdain and sclin pins cause minimal dis- turbance on the backplane busses when they make con- tact with the connector. figure 6 shows the ltc4300-2 in a compactpci configu- ration. the ltc4300-2 receives its v cc voltage from one of the long early power pins. because this power is not switched, add a 5 w to 10 w resistor between the v cc pins of the connector and the ltc4300-2, as shown in the figure. in addition, make sure that the v cc bypassing on the backplane is large compared to the 0.01 m f bypass capacitor on the card. establishing early power v cc en- sures that the 1v precharge voltage is present at the sdain and sclin pins before they make contact. connect v cc2 to the output of one of the compactpci power supply hot swap circuits. v cc2 is monitored by a filtered uvlo circuit. with the v cc2 voltage powering up after all other pins have established connection, the uvlo circuit en- sures that the backplane and card data and clock busses are not connected until the transients associated with hot swapping have settled. figure 7 shows the LTC4300-1 in a pci application, where all of the pins have the same length. in this case, connect an rc series circuit on the i/o card between v cc and enable. an rc product of 10ms provides a filter to prevent the LTC4300-1 from becoming activated until the transients associated with hot swapping have settled. figure 8 shows the ltc4300-2 in an application where the user has a custom connector with pins of three different lengths available. making v cc2 the shortest pin ensures that all other pins are firmly connected before v cc2 receives any voltage. a filtered uvlo circuit on v cc2 ensures that the v cc2 pin is firmly connected before the ltc4300-2 connects the backplane to the card. repeater/bus extender application users who wish to connect two 2-wire systems separated by a distance can do so by connecting two LTC4300-1s back-to-back, as shown in figure 9. the i 2 c specification allows for 400pf maximum bus capacitance, severely limiting the length of the bus. the smbus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise- and fall-time specifica- tions are to be met. the strong pull-up and pull-down impedances of the LTC4300-1 are capable of meeting rise- and fall-time specifications for one nanofarad of capaci- tance, thus allowing much more interconnect distance. in this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed v ol specifica- tion with respect to the ground at the other end. in addition, the connection circuitry offset voltages of the back-to-back LTC4300-1s add together, directly contrib- uting to the same problem. systems with disparate supply voltages (LTC4300-1) in large 2-wire systems, the v cc voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. this situation is well modelled by a series resistor in the v cc line, as shown in figure 10. for proper operation of the LTC4300-1, make sure that v cc(bus) 3 v cc(ltc4300) C 0.5v. 5v to 3.3v level translator and power supply redundancy (ltc4300-2) systems requiring different supply voltages for the backplane side and the card side can use the ltc4300-2, as shown in figure 11. the pull-up resistors on the card side connect from sdaout to sclout to v cc2 , and those on the backplane side connect from sdain and sclin to v cc . the ltc4300-2 functions for voltages ranging from 2.7v to 5.5v on both v cc and v cc2 . there is no constraint on the voltage magnitudes of v cc and v cc2 with respect to each other. this application also provides power supply redundancy. if either the v cc or v cc2 voltage falls below its uvlo threshold, the ltc4300-2 disconnects the backplane from the card, so that the side that is still powered can continue to function.
LTC4300-1/ltc4300-2 12 sn430012 430012fs figure 5. hot swapping multiple i/o cards into a backplane using the LTC4300-1 in a compactpci system staggered connector r13 10k r12 10k r14 10k i/o peripheral card n enable sdain sclin LTC4300-1 u3 v cc gnd cardn_scl cardn_sda sdaout sclout ready enable sdain sclin v cc gnd sdaout sclout ready enable sdain sclin v cc gnd sdaout sclout ready 4300-1/2 f05 ? ? r9 10k r8 10k r10 10k i/o peripheral card 2 LTC4300-1 u2 card2_scl card2_sda staggered connector staggered connector r5 10k r4 10k r6 10k i/o peripheral card 1 LTC4300-1 u1 card_scl card_sda r1 10k v cc r2 10k backplane backplane connector sda bd_sel scl note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 c1 0.01 f c3 0.01 f c5 0.01 f power supply hot swap power supply hot swap power supply hot swap applicatio s i for atio wu u u
LTC4300-1/ltc4300-2 13 sn430012 430012fs applicatio s i for atio wu u u figure 6. hot swapping multiple i/o cards into a backplane using the ltc4300-2 in a compactpci system c1 0.01 f c3 0.01 f c5 0.01 f r13 10k r12 10k r14 10k i/o peripheral card n v cc sdain sclin ltc4300-2 u3 v cc2 gnd cardn_scl cardn_sda sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc 4300-1/2 f06 ? ? r9 10k r8 10k r10 10k i/o peripheral card 2 ltc4300-2 u2 card2_scl card2_sda r5 10k r4 10k r6 10k i/o peripheral card 1 ltc4300-2 u1 c2 0.01 f 5.1 card_scl card_sda v cc2 backplane backplane connector sda scl note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 v cc bd_sel staggered connector staggered connector staggered connector power supply hot swap c4 0.01 f 5.1 power supply hot swap c6 0.01 f 5.1 power supply hot swap r1 10k r2 10k
LTC4300-1/ltc4300-2 14 sn430012 430012fs applicatio s i for atio wu u u figure 7. hot swapping multiple i/o cards into a backplane using the LTC4300-1 in a pci system r3 100k enable sdain sclin v cc gnd sdaout sclout ready enable sdain sclin v cc gnd sdaout sclout ready 4300-1/2 f07 r9 10k r8 10k r10 10k i/o peripheral card 2 LTC4300-1 u2 card2_scl card2_sda r5 10k r4 10k i/o peripheral card 1 LTC4300-1 u1 c2 0.1 f r7 100k c4 0.1 f card_scl card_sda r1 10k v cc r2 10k backplane backplane connector sda scl note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 c1 0.01 f c3 0.01 f r6 10k figure 8. hot swapping multiple i/o cards into a backplane using the ltc4300-2 with a custom connector staggered connector v cc sdain sclin v cc2 gnd sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc 4300-1/2 f08 r9 10k r8 10k i/o peripheral card 2 ltc4300-2 u2 card2_scl card2_sda staggered connector r5 10k r4 10k i/o peripheral card 1 ltc4300-2 u1 c2 0.01 f c4 0.01 f card_scl card_sda r1 10k r2 10k v cc2 backplane backplane connector sda scl note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 v cc c1 0.01 f c3 0.01 f r10 10k r6 10k
LTC4300-1/ltc4300-2 15 sn430012 430012fs information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. applicatio s i for atio wu u u r1 10k r3 5.1k r5 10k r2 5.1k v cc = 5v r4 10k r7 10k r8 10k 2-wire system 1 enable sdain sclin LTC4300-1 gnd v cc c1 0.01 f sdaout sclout ready scl1 to other system 1 devices sda1 c2 0.01 f r6 10k 2-wire system 2 LTC4300-1 enable sdain sclin 4300-1/2 f07 sdaout sclout ready long distance bus v cc scl1 sda1 to other system 2 devices gnd v cc note: application assumes bus capacitances within ?roper operation?region of figure 4 figure 9. repeater/bus extender application package descriptio n u ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 1001 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.65 (.0256) bcs 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.88 0.1 (.192 .004) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc
LTC4300-1/ltc4300-2 16 sn430012 430012fs ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com lt/tp 0602 2k ? printed in usa related parts part number description comments ltc1380/ltc1393 single-ended 8-channel/differential 4-channel analog low r on : 35 w single-ended/70 w differential, mux with smbus interface expandable to 32 single or 16 differential channels ltc1427-50 micropower, 10-bit current output dac precision 50 m a 2.5% tolerance over temperature, with smbus interface 4 selectable smbus addresses, dac powers up at zero or midscale ltc1623 dual high side switch controller with smbus interface 8 selectable addresses/16-channel capability ltc1663 smbus interface 10-bit rail-to-rail micropower dac dnl < 0.75lsb max, 5-lead sot-23 package ltc1694/ltc1694-1 smbus accelerator improved smbus/i 2 c rise-time, ensures data integrity with multiple smbus/i 2 c devices lt1786f smbus controlled ccfl switching regulator 1.25a, 200khz, floating or grounded lamp configurations ltc1695 smbus/i 2 c fan speed controller in thinsot tm 0.75 w pmos 180ma regulator, 6-bit dac ltc1840 dual i 2 c fan speed controller two 100 m a 8-bit dacs, two tach inputs, four gpi0 thinsot is a trademark of linear technology corporation. figure 10. system with disparate v cc voltages r1 10k v cc r2 10k r drop v cc_low sda scl 4300-1/2 f08 r4 10k r5 10k r3 10k sdain enable sclin LTC4300-1 u1 v cc gnd scl2 sda2 sdaout sclout ready c2 0.01 f note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 figure 11. 5v to 3.3v level translator v cc2 gnd sdaout sclout sdain sclin acc v cc r2 10k r3 10k card_v cc , 3v card_scl card_sda c2 0.01 f c1 0.01 f r1 10k v cc 5v r4 10k ltc4300-2 u1 scl scl 4300-1/2 f09 note: application assumes bus capacitances within ?roper operation?region of figures 3 and 4 typical applicatio s u

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